#ChipScope Core Inserter Project File Version 3.0
#Sat May 14 13:48:35 CST 2016
Project.device.designInputFile=E\:\\Projects\\NaiveMIPS-HDL\\xilinx\\NaiveMIPS\\soc_toplevel_cs.ngc
Project.device.designOutputFile=E\:\\Projects\\NaiveMIPS-HDL\\xilinx\\NaiveMIPS\\soc_toplevel_cs.ngc
Project.device.deviceFamily=18
Project.device.enableRPMs=true
Project.device.outputDirectory=E\:\\Projects\\NaiveMIPS-HDL\\xilinx\\NaiveMIPS\\_ngo
Project.device.useSRL16=true
Project.filter.dimension=13
Project.filter<0>=cpu/pc*
Project.filter<10>=cpu/
Project.filter<11>=
Project.filter<12>=clk
Project.filter<1>=cpu/if_*
Project.filter<2>=cpu/cp0*
Project.filter<3>=cpu/exception/*
Project.filter<4>=cpu/cp0_*
Project.filter<5>=cpu/excep*
Project.filter<6>=cpu/mm_*
Project.filter<7>=cpu/mm*
Project.filter<8>=cpu*
Project.filter<9>=cpu
Project.icon.boundaryScanChain=1
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=1
Project.unit<0>.clockChannel=clk
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataDepth=1024
Project.unit<0>.dataEqualsTrigger=true
Project.unit<0>.dataPortWidth=38
Project.unit<0>.enableGaps=false
Project.unit<0>.enableStorageQualification=true
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerChannel<0><0>=cpu/mm_iaddr_exp_exl
Project.unit<0>.triggerChannel<0><10>=cpu/pc_instance/pc_reg<4>
Project.unit<0>.triggerChannel<0><11>=cpu/pc_instance/pc_reg<5>
Project.unit<0>.triggerChannel<0><12>=cpu/pc_instance/pc_reg<6>
Project.unit<0>.triggerChannel<0><13>=cpu/pc_instance/pc_reg<7>
Project.unit<0>.triggerChannel<0><14>=cpu/pc_instance/pc_reg<8>
Project.unit<0>.triggerChannel<0><15>=cpu/pc_instance/pc_reg<9>
Project.unit<0>.triggerChannel<0><16>=cpu/pc_instance/pc_reg<10>
Project.unit<0>.triggerChannel<0><17>=cpu/pc_instance/pc_reg<11>
Project.unit<0>.triggerChannel<0><18>=cpu/pc_instance/pc_reg<12>
Project.unit<0>.triggerChannel<0><19>=cpu/pc_instance/pc_reg<13>
Project.unit<0>.triggerChannel<0><1>=cpu/mm_iaddr_exp_illegal
Project.unit<0>.triggerChannel<0><20>=cpu/pc_instance/pc_reg<14>
Project.unit<0>.triggerChannel<0><21>=cpu/pc_instance/pc_reg<15>
Project.unit<0>.triggerChannel<0><22>=cpu/pc_instance/pc_reg<16>
Project.unit<0>.triggerChannel<0><23>=cpu/pc_instance/pc_reg<17>
Project.unit<0>.triggerChannel<0><24>=cpu/pc_instance/pc_reg<18>
Project.unit<0>.triggerChannel<0><25>=cpu/pc_instance/pc_reg<19>
Project.unit<0>.triggerChannel<0><26>=cpu/pc_instance/pc_reg<20>
Project.unit<0>.triggerChannel<0><27>=cpu/pc_instance/pc_reg<21>
Project.unit<0>.triggerChannel<0><28>=cpu/pc_instance/pc_reg<22>
Project.unit<0>.triggerChannel<0><29>=cpu/pc_instance/pc_reg<23>
Project.unit<0>.triggerChannel<0><2>=cpu/mm_iaddr_exp_invalid
Project.unit<0>.triggerChannel<0><30>=cpu/pc_instance/pc_reg<24>
Project.unit<0>.triggerChannel<0><31>=cpu/pc_instance/pc_reg<25>
Project.unit<0>.triggerChannel<0><32>=cpu/pc_instance/pc_reg<26>
Project.unit<0>.triggerChannel<0><33>=cpu/pc_instance/pc_reg<27>
Project.unit<0>.triggerChannel<0><34>=cpu/pc_instance/pc_reg<28>
Project.unit<0>.triggerChannel<0><35>=cpu/pc_instance/pc_reg<29>
Project.unit<0>.triggerChannel<0><36>=cpu/pc_instance/pc_reg<30>
Project.unit<0>.triggerChannel<0><37>=cpu/pc_instance/pc_reg<31>
Project.unit<0>.triggerChannel<0><38>=
Project.unit<0>.triggerChannel<0><39>=
Project.unit<0>.triggerChannel<0><3>=cpu/mm_iaddr_exp_miss
Project.unit<0>.triggerChannel<0><4>=cpu/mm_daddr_exp_miss
Project.unit<0>.triggerChannel<0><5>=cpu/mm_daddr_exp_illegal_mm_alignment_err_OR_921_o
Project.unit<0>.triggerChannel<0><6>=cpu/exception_flush
Project.unit<0>.triggerChannel<0><7>=cpu/cp0_user_mode
Project.unit<0>.triggerChannel<0><8>=cpu/pc_instance/pc_reg<2>
Project.unit<0>.triggerChannel<0><9>=cpu/pc_instance/pc_reg<3>
Project.unit<0>.triggerConditionCountWidth=0
Project.unit<0>.triggerMatchCount<0>=1
Project.unit<0>.triggerMatchCountWidth<0><0>=0
Project.unit<0>.triggerMatchType<0><0>=1
Project.unit<0>.triggerPortCount=1
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortWidth<0>=38
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=1
Project.unit<0>.type=ilapro
